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MC68HC68t1 motorola 1 cmos the m c68hc68t 1 h cmo s c lock/ra m p eriphera l c ontain s a r ealtime clock/calendar, a 32 x 8 static ram, and a synchronous, serial, threewire interface for communication with a microcontroller or processor. operating in a burst mode, successive clock/ram locations can be read or written using only a s ingl e s tartin g a ddress . a n o nchip o scillato r a llow s a cceptanc e o f a selectable crystal frequency or the device can be programmed to accept a 50/60 hz line input frequency. the l in e a n d s yste m v oltag e ( v sys ) p in s g iv e t h e m c68hc68t1 t he capability for sensing powerup/powerdown conditions, a capability useful for batterybackup s ystems . t h e d evic e h a s a n i nterrup t o utpu t c apabl e o f signaling a microcontroller or processor of an alarm, periodic interrupt, or power sense condition. an alarm can be set for comparison with the seconds, minutes, and hours registers. this alarm can be used in conjunction with the power supply enable (pse) output to initiate a system powerup sequence if the v sys pin is powered to the proper level. a software powerdown sequence can be initiated by setting a bit in the interrupt control register . this applies a reset to the cpu via the cpur pin, sets the clock out (clkout) and pse pins low , and disables the serial interface. this condition is held until a rising edge is sensed on the v sys input pin, signaling system power coming on, or by activation of a previously enabled interrupt if the v sys pin is powered up. a w atchdo g c ircui t c a n b e e nable d t ha t r equire s t h e m icrocontroller o r processor to toggle the slave select (ss) pin of the MC68HC68t1 periodically without performing a serial transfer . if this condition is not met, the cpur line resets the cpu. ? full clock features e seconds, minutes, hours (am/pm), dayofweek, date, month, year (0 99), auto leap year ? 32byte general purpose ram ? direct interface to motorola spi and national microwire serial data ports ? minimum timekeeping voltage: 2.2 v ? burst mode for reading/writing successive addresses in clock/ram ? selectable crystal or 50/60 hz line input frequency ? clock registers utilize bcd data ? buffered clock output for driving cpu clock, timer, colon, or lcd backplane ? poweron reset with first timeup bit ? freeze circuit eliminates software overhead during a clock read ? three independent interrupt modes e alarm, periodic, or powerdown ? cpu reset output e provides orderly powerup/powerdown ? watchdog circuit ? pinforpin replacement for cdp68hc68t1 ? chip complexity: 8500 fets or 2125 equivalent gates ? also see application notes ane425 ause of the MC68HC68t1 rtc with m6805 microprocessoro, an457 aproviding a realtime clock for the mc68302o, and an1065 ause of the MC68HC68t1 realtime clock with multiple time baseso microwire is a trademark of national semiconductor inc. order this document by MC68HC68t1/d
semiconductor technical data pin assignment p suffix plastic dip case 648 dw suffix sog package case 751g ordering information MC68HC68t1p plastic dip MC68HC68t1dw sog package 16 1 16 1 13 14 15 16 9 10 11 12 5 4 3 2 1 8 7 6 v sys v batt xtal in xtal out v dd pse por line sck int cpur clkout v ss ss miso mosi ? motorola, inc. 1996 rev 2 2/96
MC68HC68t1 motorola 2 oscillator prescale second minute hour day/ date month am/pm and hour logic calendar logic 50/60 hz stop /start prescale select clock select clock control reg interrupt control reg 8bit data bus comparator year second latch minute latch hour latch clock and int logic status register power sense control serial interface freeze circuit 32 x 8 ram pin 16 = v dd pin 8 = v ss xtal in xtal out v batt line clkout int v sys por pse cpur sck miso mosi ss 12 10 14 15 13 11 1 3 9 2 4 6 5 7 block diagram
MC68HC68t1 motorola 3 absolute maximum ratings* (voltages referenced to v ss ) symbol parameter value unit v dd dc supply voltage 0.5 to + 7.0 v v in dc input voltage (except line input**) 0.5 to v dd + 0.5 v v out dc output voltage 0.5 to v dd + 0.5 v i in dc input current, per pin 10 ma i out dc output current, per pin 10 ma i dd dc supply current, v dd and v ss pins 30 ma p d power dissipation, per package*** 500 mw t stg storage temperature 65 to + 150 c t l lead t emperature (10second soldering) 260 c * maximum ratings are those values beyond which damage to the device may occur . ** see electrical characteristics table. *** power dissipation temperature derating: ? 12 mw/ c from 65 to 85 c. electrical characteristics (t a = 40 to + 85 c, voltages referenced to v ss ) symbol parameter test condition v dd v guaranteed limit unit v dd power supply voltage range e 3.0 to 6.0 v v (stdby) minimum standby (timekeeping) voltage* e 2.2 v v il maximum lowlevel input voltage 3.0 4.5 6.0 0.9 1.35 1.8 v v ih minimum highlevel input voltage 3.0 4.5 6.0 2.1 3.15 4.2 v v in maximum input voltage, line input power sense mode 5.0 12 v pp v ol maximum lowlevel output voltage i out = 0 a i out = 1.6 ma 4.5 0.1 0.4 v v oh minimum highlevel output voltage i out = 0 a i out = 1.6 ma 4.5 4.4 3.7 v i in maximum input current, except ss v in = v dd or v ss 6.0 1 a i il maximum lowlevel input current, ss v in = v ss 6.0 1.0 a i ih maximum pulldown current, ss v in = v dd 6.0 100 a i oz maximum threestate leakage current v out = v dd or v ss 6.0 10 a i dd maximum quiescent supply current v in = v dd or v ss , all input; i out = 0 a 6.0 50 a i dd maximum rms operating supply current crystal operation i out = 0 a, f xtal in = 32 khz v in = v dd or v ss , all f xtal in = 1 mhz inputs except xtal in , f xtal in = 2 mhz clock out disabled, f xtal in = 4 mhz no serial access cycles 5.0 0.1 0.6 0.84 1.2 ma maximum rms operating supply current external frequency source driving xtal in , xtal out open i out = 0 a, f xtal in = 32 khz v in = v dd or v ss , f xtal in = 1 mhz clock out disabled, f xtal in = 2 mhz no serial access f xtal in = 4 mhz cycles 5.0 0.024 0.12 0.24 0.5 i batt maximum rms standby current crystal operation v batt = 3.0 v, f xtal in = 32 khz v sys = 0.0 v, f xtal in = 1 mhz v dd = 0.0 v, f xtal in = 2 mhz i out = 0 a, f xtal in = 4 mhz v in = don't care, all inputs except xtal in , clock out disabled, no serial access cycles 0.0 25 250 360 600 a * timekeeping function only , no read/write accesses. data in the registers and ram retained. this device contains circuitry to protect the inputs against damage due to high static voltages or electric fields. however , pre - cautions must be taken to avoid applications of any voltage higher than maximum rated volt - ages to this highimpedance circuit. for proper operation, v in and v out should be constrained to the range v ss (v in or v out ) v dd . unused inputs must always be tied to an appropriate logic voltage level (e.g., either v ss or v dd ). unused outputs must be left open.
MC68HC68t1 motorola 4 ac electrical characteristics (t a = 40 to + 85 c, c l = 200 pf, input t r = t f = 6 ns, voltages referenced to v ss ) symbol parameter figure no. v dd v guaranteed limit unit f sck maximum clock frequency (refer to sck t w , below) 1, 2, 3 3.0 4.5 6.0 e 2.1 2.1 mhz t plh , t phl maximum propagation delay, sck to miso 2, 3 3.0 4.5 6.0 200 100 100 ns t plz , t phz maximum propagation delay, ss to miso 2, 4 3.0 4.5 6.0 200 100 100 ns t pzl , t pzh maximum propagation delay, sck to miso 2, 4 3.0 4.5 6.0 200 100 100 ns t tlh , t thl maximum output transition t ime, any output (measured between 70% v dd and 20% v dd ) 2, 3 3.0 4.5 6.0 200 100 100 ns c in maximum input capacitance e 10 pf timing requirements (t a = 40 to + 85 c, input t r = t f = 6 ns, voltages referenced to v ss ) symbol parameter figure no. v dd v guaranteed limit unit t su minimum setup time, ss to sck 1, 2 3.0 4.5 6.0 200 100 100 ns t su minimum setup time, mosi to sck 1, 2 3.0 4.5 6.0 200 100 100 ns t h minimum hold time, sck to ss 1, 2 3.0 4.5 6.0 250 125 125 ns t h minimum hold time, sck to mosi 1, 2 3.0 4.5 6.0 200 100 100 ns t rec minimum recovery time, sck 1, 2 3.0 4.5 6.0 200 200 200 ns t w(h) , t w(l ) minimum pulse width, sck 1, 2 3.0 4.5 6.0 400 200 200 ns t w minimum pulse width, por 3.0 4.5 6.0 e 100 100 ns t r , t f maximum input rise and fall times (except xtal in and por ) (measured between 70% v dd and 20% v dd ) 1, 2 3.0 4.5 6.0 e 2 2 s
MC68HC68t1 motorola 5 mosi sck ss t su t w(l) t r t w(h) 1/f sck t h t rec t h t su t f a6 a5 a0 d7 o d6 o d0 n note: measurement points are v il and v ih unless otherwise noted on the ac electrical characteristics table. e v dd e v ss e v dd e v ss e v dd e v ss d1 n w/r figure 1. write cycle mosi sck ss t su t w(l) t r t w(h) 1/f sck t h t rec t h w/r a6 a5 a0 d6 o d0 n note: measurement points are v ol , v oh , v il , and v ih unless otherwise noted on the ac electrical characteristics table. e v dd e v ss e v dd e v ss e v dd e v ss d1 n d7 o miso t su t f t tlh , t thl t plz , t phz t plh , t phl tp zl , tp zh high impedance figure 2. read cycle device under test output test point c l * * includes all probe and fixture capacitance. device under test output test point c l * * includes all probe and fixture capacitance. connect to v dd when testing t plz and t pzl connect to v ss when testing t phz and t pzh figure 3. test circuit figure 4. test circuit
MC68HC68t1 motorola 6 operating characteristics the r ealtim e c loc k c onsist s o f a c lock/calenda r a n d a 32 x 8 ram (see figure 5). communication with the device may be established via a serial peripheral interface (spi) or microwire bus. in addition to the clock/calendar data from seconds t o y ears , a n d s ystem s f lexibilit y p rovide d b y t he 32byte ram, the clock features computer handshaking with an interrupt output and a separate squarewave clock output that can be one of seven dif ferent frequencies. an alarm cir- cuit is available that compares the alarm latches with the se - conds, minutes, and hours time counters and activates the interrupt output when they are equal. the clock is specifically designed to aid in powerup/powerdown applications and offers several pins to aid the designer of batterybackup sys - tems. clock/calendar the clock/calendar portion of this device consists of a long string of counters that is toggled by a 1 hz input. the 1 hz input is derived from the onchip oscillator that utilizes one of four possible external crystals or that can be driven by an ex - ternal frequency source. the 1 hz trigger to the counters can also be supplied by a 50 or 60 hz source that is connected to the line input pin. the time counters offer seconds, minutes, and hours data in 12 or 24hour format. an am/pm indicator is available that once set, toggles at 12:00 am and 12:00 pm. the calen - dar counters consist of day of week, date of month, month, and year information. data in the counters is in bcd format. the hours counter utilizes bcd for hours data plus bits for 12/24 hour and am/pm modes. the seven time counters are read serially at addresses $20 through $26. the time count- ers are written to at addresses $a0 through $a6. (see fig - ures 5 and 6 and table 1.) 32 x 8 generalpurpose ram the realtime clock also has a static 32 x 8 ram. the ram is read at addresses $00 through $1f and written to at addresses $80 through $9f (see figure 5). alarm the alarm is set by accessing the three alarm latches and loading the desired data. (see serial peripheral interface .) the alarm latches consist of seconds, minutes, and hours registers. w he n t hei r o utput s e qua l t h e v alue s o f t h e s e- conds, minutes, and hours time counters, an interrupt is gen - erated. the interrupt output goes low if the alarm bit in the status register is set and the interrupt output is activated after an alarm time is sensed (see pin descriptions, int pin ). to preclude a false interrupt when loading the time counters, the alarm interrupt bit in the interrupt control register should be reset. this procedure is not required when the alarm time is being loaded. watchdog function when w atchdog (bit 7) in the interrupt control register is set high, the clock' s slave select pin must be toggled at regu - lar intervals without a serial data transfer . if ss is not toggled at the rate shown in t able 2, the MC68HC68t1 supplies a cpu reset pulse at pin 2 and w atchdog (bit 6) in the status register is set (see figure 7). typical service and reset times are shown in table 2. clock out the value in the three least significant bits of the clock contro l r egiste r s elect s o n e o f s eve n p ossibl e o utpu t f re- quencies. (see clock control register .) this squarewave signal i s a vailabl e a t t h e c lkou t p in . w he n t h e p ower down operation is initialized, the output is reset low. control register and status register the operation of the realtime clock is controlled by the clock control and interrupt control registers, which are read/ write registers. another register , the status register , is avail - able to indicate the operating conditions. the status register is a readonly register , and a read operation resets status bits. mode select the voltage level that is present at the v sys input pin at the end of poweron reset selects the device to be in the single supply mode or batterybackup mode. singlesupply mode if v sys is powered up when poweron reset is completed; clkout, pse, and cpur are enabled high and the device is completely operational. cpur is asserted low if the volt - age level at the v sys pin subsequently falls below v batt + 0.7 v . if clkout , pse, and cpur are reset low due to a powerdown instruction, v sys brought low and then pow - ered high reenables these outputs. an example of the singlesupply mode is where only one supply is available and v dd , v batt , and v sys are tied to- gether to the supply. batterybackup mode if v sys is not powered up (v sys = 0 v) at the end of pow - eron r eset , c lkout , p se , c pur , a n d s s a r e d isabled (clkout, pse, and cpur low). this condition is held until v sys rises to a threshold (approximately 0.7 v) above v batt . clkout, pse, and cpur are then enabled and the device is operational. if v sys falls below a threshold above v batt , the outputs clkout, pse, and cpur are reset low. an example of batterybackup operation occurs if v sys is tied to the 5 v supply and is not receiving voltage from a sup - ply. a rechargeable battery is connected to the v batt pin, causing a por while v sys = 0 v . the device retains data and keeps time down to a minimum v batt voltage of 2.2 v. the power consumption may not settle to the specified lim - it until main power is cycled once. power control power c ontro l i s c ompose d o f t w o o perations , p ower sense and powerdown/powerup. t wo pins are involved in power sensing, the line input pin and the int output pin. two a dditiona l p ins , p se a n d v sys , a r e u tilize d d uring powerdown/powerup operation.
MC68HC68t1 motorola 7 freeze function the f reez e f unctio n p revent s a n i ncremen t o f t h e t ime counters, if any of the registers are being read. also, alarm operation i s d elaye d i f t he r egister s a r e b ein g r ead . t his causes the clock to lose time with increasing rates of accel - eration. power sensing when power sensing is enabled (power sense bit in the interrupt control register), ac/dc transitions are sensed at the line input pin. threshold detectors determine when tran - sitions cease. after a delay of 2.68 to 4.64 ms plus the exter- nal input rc circuit time constant, an interrupt true bit is set high in the status register . this bit can then be sampled to see if system power has turned back on (see figure 8). the powersense circuitry operates by sensing the level of the voltage present at the line input pin. this voltage is cen - tered around v dd , and as long as the voltage is either plus or minus a threshold (approximately 0.7 v) from v dd , a power sense f ailur e i s n o t i ndicated . w it h a n a c s igna l p resent, remaining in this v dd window longer than a maximum of 4.64 ms activates the powersense circuit. the larger the amplitude of the signal, the less likely a power failure would be detected. a 50 or 60 hz, 10 v pp sinewave voltage is an acceptable signal to present at the line input pin to set up the powersense function. when ac power fails, an inter- nal circuit pulls the voltage at the line pin within the detection window. powerdown powerdown i s a p rocessordirecte d o peration. t he powerdown bit is set in the interrupt control register to initi - ate powerdown operation. during powerdown, the power supply enable (pse) output, normally high, is driven low . the clkout pin is driven low . the cpur output, connected to the processor reset input pin, is also driven low . in addition, the serial interface (mosi and miso) is disabled (see fig - ure 9). powerup there a r e f ou r m ethods t ha t c a n i nitiat e t h e p owerup mode. two of the methods require an interrupt to the micro - controller or processor by programming the interrupt control register. the interrupts can be generated by the alarm circuit by setting the alarm bit and the appropriate alarm registers. also, an interrupt can be generated by programming the peri - odic interrupt bits in the interrupt control register . v sys must be at 5 volts for this operation to occur. the third method is by initiating the power sense circuit with the power sense bit in the interrupt control register set to sense power loss along with the v sys pin to sense subse - quent powerup condition (see figure 10). (reference fig - ure 19 for application circuit for third method.) the fourth method that initiates powerup occurs when the level on the v sys pin rises 0.7 v above the level of the v batt pin, after previously falling to the level of v batt while in the batterybackup mode. an interrupt is not generated when the fourth method is utilized. while i n t h e s inglesuppl y m ode, p oweru p i s i nitiated when the v sys pin loses power and then returns high. there is no interrupt generated when using this method (see fig - ure 11).
MC68HC68t1 motorola 8 seconds minutes hours day of the week date of the month month year not used not used not used not used not used not used not used not used not used status register clock control register interrupt control register $20 $21 $22 $23 $24 $25 $26 $27 $28 $29 $2a $2b $2c $2d $2e $2f $30 $31 $32 $00 $1f $20 $32 $33 $7f $80 $9f $a0 $b2 t h r u t h r u t h r u t h r u t h r u write addresses only write addresses only not used read addresses only read addresses only 32 bytes generalpurpose user 32 bytes generalpurpose user ram clock/calendar ram hexadecimal seconds minutes hours day of the week date of the month month year not used seconds alarm minutes alarm hours alarm not used not used not used not used not used not used clock control register interrupt control register $a0 $a1 $a2 $a3 $a4 $a5 $a6 $a7 $a8 $a9 $aa $ab $ac $ad $ae $af $b0 $b1 $b2 hexadecimal hexadecimal clock/calendar figure 5. address map
MC68HC68t1 motorola 9 $a0 $a1 $a2 $a3 $a4 $a5 $a6 $b1 $b2 tens 0 5 tens 0 5 tens 0 3 tens 0 1 tens 0 9 units 0 9 units 0 9 units 0 9 units 1 7 units 0 9 units 0 9 units 0 9 $20 $21 $22 $23 $24 $25 $26 $31 $32 read write hex address read/write registers db7 db0 12 hr 24 pm/am tens 0 2 x x x x x x 7 6 5 4 3 2 1 0 writeonly registers readonly register ram data byte $a8 $a9 $aa n/a n/a n/a n/a $b0 $00 t0 $1f $80 t0 $9f function seconds (00 59) minutes (00 59) db7, 1 = 12 hr, 0 = 24 hr db5, 1 = pm, 0 = am hours (01 12 or 00 23) day of week (01 07) sunday = 1 month (01 12) jan = 1 date of month (01 31) year (00 99) clock control register interrupt control register seconds alarm (00 59) minutes alarm (00 59) hours alarm (01 21 or 00 23) db5, 1 = pm, 0 = am in 12 hr mode status register data 7 6 5 4 3 2 1 0 d7 d6 d5 d4 d3 d2 d1 d0 units 0 9 units 0 9 units 0 9 tens 0 5 tens 0 5 pm/am tens 0 2 x x note: x = don't care for write x = 0 for read n/a = not applicable figure 6. clock/ram registers 7 6 5 4 3 2 1 0
MC68HC68t1 motorola 10 table 1. clock/calendar and alarm data modes address location read write function decimal range bcd data range bcd date* example $20 $a0 seconds 0 59 00 59 21 $21 $a1 minutes 0 59 00 59 40 $22 $a2 hours** (12 hour mode) 1 12 81 92 (am) a1 b2 (pm) 90 hours (24 hour mode) 0 23 00 23 10 $23 $a3 day of week (sunday = 1) 1 7 01 07 03 $24 $a4 date of month 1 31 01 31 16 $25 $a5 month (jan = 1) 1 12 01 12 06 $26 $a6 year 0 99 00 99 87 n/a $a8 seconds alarm 0 59 00 59 21 n/a $a9 minutes alarm 0 59 00 59 40 n/a $aa hours alarm*** (12 hour mode) 1 12 01 12 (am) 21 32 (pm) 10 hours alarm (24 hour mode) 0 23 00 23 10 n/a = not applicable * example: 10:40:21 am, tuesday, june 16, 1987. ** most significant data bit, d7, is a0o for 24hour mode and a1o for 12hour mode. data bit d5 is a1o for pm and a0o for am in 12hour mode. *** data bit d5 is a1o for pm and a0o for am in 12hour mode. data bits d7 and d6 are don't cares. table 2. watchdog service and reset times 50 hz 60 hz xtal min max min max min max service time e 10 ms e 8.3 ms e 7.8 ms reset time 20 ms 40 ms 16.7 ms 33.3 ms 15.6 ms 31.3 ms note: reset does not occur immediately after slave select is toggled. approximately two clock cycles later , reset initiates. service time service time ss sck cpur figure 7. watchdog operation waveforms
MC68HC68t1 motorola 11 v dd 0 v v dd xtal in xtal out line msb lsb 1 realtime clock MC68HC68t1 int v dd irq mc68hc05c4 cpu note: a 60 hz, 10 v pp sinewave voltage is an acceptable signal to present at the line input pin. figure 8. power sensing functional diagram (status register) interrupt control register msb lsb 1 realtime clock MC68HC68t1 v dd reset mc68hc05c4 cpu osc 1 cpur serial interface clkout pse miso mosi to system power control figure 9. software powerdown functional diagram v sys v batt
MC68HC68t1 motorola 12 mosi realtime clock MC68HC68t1 serial interface cpur pse power sense circuit periodic interrupt signal alarm circuit powerup clkout miso int note: the v sys pin must be powered up. internal interrupt signal figure 10. powerup functional diagram (initiated by internal interrupt signal generation) mosi realtime clock MC68HC68t1 serial interface cpur pse clkout miso v sys v batt backup switch power switch/ mode control v batt v dd figure 11. powerup functional diagram (initiated by a rise in voltage on the v sys pin)
MC68HC68t1 motorola 13 pin descriptions clkout clock output (pin 1) this signal is the buf fered clock output which can provide one of the seven selectable frequencies (or this output can be reset low). the contents of the three least significant bit positions in the clock control register determine the output frequency (50% duty cycle, except 2 hz in the 50 hz time base mode). during powerdown operation (powerdown bit in the interrupt control register set high), the clkout pin is reset low. cpur cpu reset (pin 2) this pin provides an n channel, opendrain output and requires an external pullup resistor . this active low output can be used to drive the reset pin of a microprocessor to per - mit orderly powerup/powerdown. the cpur output is low from 15 to 40 ms when the watchdog function detects a cpu failure (see table 2). the low level time is determined by the input frequency source selected as the time standard. cpur is reset low when powerdown is initiated. int interrupt (pin 3) this activelow output is driven from a single n channel transistor a n d m us t b e t ie d t o a n e xterna l p ullup r esistor. interrupt is activated to a low level when any one of the fol - lowing takes place: 1. power sense operation is selected (power sense bit in the interrupt control register is set high) and a power failure occurs. 2. a previously set alarm time occurs. the alarm bit in the status r egiste r a nd t h e i nterrup t s igna l a r e d elayed 30.5 ms when 32 khz or 1 mhz operation is selected, 15.3 ms for 2 mhz operation, and 7.6 ms for 4 mhz operation. 3. a previously selected periodic interrupt signal activates. the status register must be read to reset the interrupt out- put after the selected periodic interval occurs. this is also true when conditions 1 and 2 activate the interrupt. if power down has been previously selected, the interrupt also sets the powerup function only if power is supplied to the v sys pin to the proper threshold level above v batt . sck serial clock (pin 4) this serial clock input is used to shift data into and out of the onchip interface logic. sck retains its previous state if the line driving it goes into a highimpedance state. in other words, if the source driving sck goes to the highimpedance state, the previous low or high level is retained by onchip control circuitry. mosi master out slave in (pin 5) the serial data present at this port is latched into the inter - face logic by sck if the logic is enabled. data is shifted in, either on the rising or falling edges of sck, with the most sig - nificant bit (msb) first. in motorola' s microcomputers with spi, the state of the cpol bit determines which is the active edge of sck. if sck is high when ss goes high, the state of the cpol bit is high. likewise, if a rising edge of ss occurs while sck is low (see figure 13), then the cpol bit in the microcomputer is low. mosi retains its previous state if the line driving it goes into h ighimpedanc e s tate . i n o the r w ords , i f t h e s ource drivin g m os i g oe s t o t h e h ighimpedanc e s tate , t h e p re- vious low or high level is retained by onchip control circuitry. miso master in slave out (pin 6) the serial data present at this port is shifted out of the interface logic by sck if the logic is enabled. data is shifted out, either on the rising or falling edge of sck, with the most significant bit (msb) first. the state of the cpol bit in the microcomputer determines which is the active edge of sck (see figure 13). ss slave select (pin 7) when high, the slave select input activates the interface logic; otherwise the logic is in a reset state and the miso pin is i n t h e h ighimpedanc e s tate . t h e w atchdo g c ircui t i s toggled a t t hi s p in . s s h a s a n i nterna l p ulldow n d evice. therefore, if ss is in a low state before going to high imped- ance, ss can be left in a highimpedance state. that is, if the source d rivin g s s g oe s t o t h e h ighimpedanc e s tate , t he previous low level is retained by onchip control circuitry. v ss ground (pin 8) this pin is connected to ground. pse power supply enable (pin 9) the power supply enable output is used to control system power and is enabled high under any one of the following conditions: 1. v sys rises above the v batt voltage after v sys is reset low by a system failure. 2. an interrupt occurs (if the v sys pin is powered up 0.7 v above v batt ). 3. a poweron reset occurs (if the v sys pin is powered up 0.7 v above v batt ). pse is reset low by writing a high into the powerdown bit of the interrupt control register. por poweron reset (pin 10) this activelow schmitttrigger input generates an inter - nal poweron reset signal using an external rc network (see figures 18 through 21). both control registers and frequency dividers for the oscillator and line inputs are reset. the status register is reset except for the first timeup bit (bit 4), which is set high. at the end of the poweron reset, singlesupply or batterybackup mode is selected at this time, determined by the state of v sys . this pin may be more aptly named firsttimeup reset.
MC68HC68t1 motorola 14 line line sense (pin 11) the line sense input can be used to drive one of two functions. the first function utilizes the input signal as the fre- quency source for the timekeeping counters. this function is selected by setting the line/xtal bit high in the clock control register. the second function enables the line input to de - tect a p owe r f ailure . t hreshol d d etector s o peratin g a bove and below v dd sense an ac voltage loss. the power sense bit i n t h e i nterrup t c ontro l r egiste r m us t b e s e t h igh, a nd crystal or external clock source operation is required. the line/xtal b i t i n t h e c loc k c ontro l r egiste r m us t b e l o w t o select crystal operation. when power sense is enabled, this pin, left unconnected, floats to v dd . this output has no esd protection diode tied to v dd which allows this pin' s voltage to rise above v dd . care must be taken in the handling of this device. v sys system voltage (pin 12) this input is connected to system voltage. the level on this pin initiates powerup if it rises 0.7 v above the level at the v batt input pin after previously falling below 0.7 v below v batt . when powerup is initiated, the pse pin returns high and the clkout pin is enabled. the cpur output pin is also set high. conversely , if the level of the v sys pin falls be - low v batt + 0.7 v , the pse, clkout , and cpur pins are placed low . the voltage level present at this pin at the end of por determines the device's operating mode. v batt battery voltage (pin 13) this pin is the only oscillator power source and should be connected to the positive terminal of the battery . the v batt pin always supplies power to the MC68HC68t1, even when the device is not in the batterybackup mode. t o maintain timekeeping, the v batt pin must be at least 2.2 v . when the level on the v sys pin falls below v batt + 0.7 v, v batt is internally connected to the v dd pin. when t h e l in e i npu t i s u se d a s t h e f requenc y s ource, the u nuse d v batt a n d x ta l p in s m a y b e t ie d t o v ss . alternatively, if v batt is connected to v dd , xtal in can be tied to either v ss or v dd . this output has no esd protection diode tied to v dd which allows this pin' s voltage to rise above v dd . care must be taken in the handling of this device. xtal in , xtal out crystal input/output (pins 14, 15) for crystal operation, these two pins are connected to a 32.768 khz, 1.048576 mhz, 2.097152 mhz, or 4.194304 mhz crystal. if crystal operation is not desired and line sense is used as frequency source, connect x tal in to v dd or v ss (caution: see v batt pin description) and leave x ta out open. if an external clock is used, connect the external clock to xtal in and leave x tal out open. the external clock must swing from at least 30 to 70% of ( v dd v ss ). preferably , this input should swing from v ss to v dd . v dd positive power supply (pin 16) for f ul l f unctionality , t h e p ositiv e p owe r s uppl y p i n m ay range from 3.0 to 6.0 v with respect to v ss . t o maintain time - keeping, the minimum standby voltage is 2.2 v with respect to v ss . fo r p rope r o peratio n i n b atterybacku p m ode , a diode must be placed in series with v dd . caution data transfer to/from the MC68HC68t1 must not be a ttempte d i f t h e s uppl y v oltag e f all s b elow 3.0 v. registers clock control register (read/write) e read address $31/write address $b1 clk out 0 clk out 2 50 hz 60 hz xtal select 1 line xtal clk out 1 xtal select 0 msb d7 lsb d0 d1 d2 d3 d4 d5 d6 all bits are reset low by a poweron reset. start stop startstop a high written into this bit enables the counter stages of clock circuitry . a low holds all bits reset in the divider chain from 32 hz to 1 hz. the clock out signal selected by bits d0, d1, and d2 is not af fected by the stop function except the 1 and 2 hz outputs. line/ xtal when this bit is high, clock operation uses the 50 or 60 cycle input present at the line input pin. when the bit is low , the xtal in pin is the source of the time update. xtal select accommodation of one of four possible crystals are se - lected by the value in bits d4 and d5. 0 = 4.194304 mhz 2 = 1.048576 mhz 1 = 2.097152 mhz 3 = 32.768 khz the MC68HC68t1 has an onchip 150 k resistor that is switched in series with the internal inverter when 32 khz is selected via the clock control register . at powerup, the de - vice sets up for a 4 mhz oscillator and the series resistor is not part of the oscillator circuit. until this resistor is switched in, oscillations may be unstable with the 32 khz crystal. (see figure 12.) xtal in xtal out realtime clock MC68HC68t1 5 30 pf c1 r2 r1 10 40 pf c2 figure 12. recommended oscillator circuit (c1, c2 values depend upon the crystal frequency)
MC68HC68t1 motorola 15 resistor r 1 i s r ecommende d t o b e 1 0 m for 3 2 k hz operation. consult crystal manufacturer for r1 value for oth- er frequencies. resistor r2 must be used in 32 khz opera - tion only . use a 200 to 300 k range. this stabilizes the oscillator until the control register is set properly and reduces standby current. 50 hz 60 hz 50 hz may be used as the input frequency at the line in- put when this bit is set high; a low accommodates 60 hz. the power sense bit in the interrupt control register must be reset low for line frequency operation. clock out three bits specify one of the seven frequencies to be used as the squarewave clock output (clkout). 0 = xtal 4 = disable (low output) 1 = xtal/2 5 = 1 hz 2 = xtal/4 6 = 2 hz 3 = xtal/8 7 = 50/60 hz for line operation 7 = 64 hz for xtal operation all bits in the clock control register are reset by a poweron reset. therefore, xtal is selected as the clock output at this time. interrupt control register (read/write) e read address $32/write address $b2 periodic select power sense power down alarm all bits are reset low by poweron reset. watch dog msb d7 lsb d0 d1 d2 d3 d4 d5 d6 watchdog when this bit is set high, the watchdog operation is en - abled. this function requires the cpu to toggle the ss pin periodically without a serial transfer requirement. in the event this does not occur , a cpu reset is issued at the cpur pin. the s tatu s r egiste r m us t b e r ea d b efor e r eenablin g t he watchdog function. powerdown a high in this location initiates a powerdown. a cpu reset occurs via the cpur output, the clkout and pse output pins are reset low, and the serial interface is disabled. power sense when set high, this bit is used to enable the line input pin to sense a power failure. when power sense is selected, the input to the 50/60 hz prescaler is disconnected; therefore, crystal operation is required. an interrupt is generated when a power failure is sensed and the power sense and interrupt true bit in the status register are set. when power sense is activated, a logic low must be written to this location followed by a high to reenable power sense. alarm the output of the alarm comparator is enabled when this bit is set high. when an equal comparison occurs between the seconds, minutes, and hours time counters and alarm latches, the interrupt output is activated. when loading the time counters, this bit should be reset low to avoid a false in - terrupt. this is not required when loading the alarm latches. see int pin description for explanation of alarm delay. periodic select the value in these four bits (d0, d1, d2, and d3) selects the frequency of the periodic output (see table 3). table 3. periodic interrupt output frequencies (at int pin) d3 d0 value (hex) periodic interrupt output frequency frequency timebase value (hex) periodic interrupt output frequency xtal line 0 disable 1 2048 hz x 2 1024 hz x 3 512 hz x 4 256 hz x 5 128 hz x 6 64 hz x 50 or 60 hz x 7 32 hz x 8 16 hz x 9 8 hz x a 4 hz x b 2 hz x x c 1 hz x x d 1 cycle per minute x x e 1 cycle per hour x x f 1 cycle per day x x status register (read only) e address $30 power sense int alarm int watch dog msb d7 lsb d0 d1 d2 d3 d4 d5 d6 clock int inter- rupt true first time up 0 0 note all bits are reset low by a poweron reset except the first timeup bit which is set high. all bits ex- cept the power sense bit are reset after a read of the status register. watchdog if this bit is set high, the watchdog circuit has detected a cpu failure. first timeup poweron reset sets this bit high. this signifies the data in the r a m a n d c lock i s n o t v ali d a n d s houl d b e i nitialized.
MC68HC68t1 motorola 16 after the status register is read, the first timeup bit is set low if the por pin is high. conversely , if the por pin is held low , the first timeup bit remains set high. interrupt true a high in this bit signifies that one of the three interrupts (power sense, alarm, or clock) is valid. powersense interrupt this bit set high signifies that the powersense circuit has generated an interrupt. this bit is not reset after a read of this register. alarm interrupt when t h e c ontent s o f t h e s econds , m inutes , a n d h ours time counters and alarm latches are equal, this bit is set high. the status register must be read before loading the interrupt control register for valid alarm indication after the alarm acti- vates. clock interrupt a periodic interrupt sets this bit high (see table 3). serial peripheral interface (spi) the s eria l p eriphera l i nterfac e ( spi ) u tilize d b y t he MC68HC68t1 is a serial synchronous bus for address and data transfers. the shift clock (sck), which is generated by the microcomputer , is active only during address and data transfer. i n s ystem s u sing t h e m c68hc05c 4 o r mc68hc11a8, the inactive clock polarity is determined by the clock polarity (cpol) bit in the microcomputer ' s control register. a unique feature of the MC68HC68t1 is that the level of the inactive clock is determined by sampling sck when ss becomes active. therefore, either sck polarity is accom - modated. input data (mosi) is latched internally on the inter - nal strobe edge and output data (miso) is shifted out on the shift edge (see t able 4 and figure 13). there is one clock for each bit transferred. address as well as data bits are trans - ferred in groups of eight. table 4. function table mode signal mode ss sck mosi miso disabled reset l input disabled input disabled highz write h cpol = 0 cpol = 1 data bit latch highz read h cpol = 0 cpol = 1 x next data bit shifted out* * miso remains at a highz until eight bits of data are ready to be shifted out during a read. miso remains at a highz during the entire write cycle. address and data format there are three types of serial transfers: 1. read or write address 2. read or write data 3. watchdog reset (actually a nontransfer) the address and data bytes are shifted msb first, into the serial data input (mosi) and out of the serial data output (miso). any transfer of data requires the address of the byte to specify a write or read clock or ram location, followed by one or more bytes of data. data is transferred out of miso for a read operation and into mosi for a write operation (see figures 14 and 15).
MC68HC68t1 motorola 17 mosi sck ss sck ss cpol = 0* cpol = 1* msb msb1 shift internal strobe shift internal strobe * cpol is a bit that is set in the microcomputer 's control register. figure 13. serial clock (sck) as a function of mcu clock polarity (cpol) mosi ?????? ?????? ?????? ?????? ?????? ??? ??? ??? ??? ??? a7 a6 a5 a4 a3 a2 a1 a0 lsb msb sck* ss * sck can be either polarity . figure 14. address byte transfer waveforms mosi ?? ?? ?? ?? ??????? ??????? ??????? ??????? d7 d6 d5 d4 d3 d2 d1 d0 lsb msb sck* ss miso ?? ?? ?? ?? ??????? ??????? ??????? ??????? d7 d6 d5 d4 d3 d2 d1 d0 lsb msb * sck can be either polarity . figure 15. read/write data transfer waveforms
MC68HC68t1 motorola 18 address byte the address byte is always the first byte entered after ss goes t rue . t o t ransmi t a n ew a ddress , s s m us t f irs t b e brought low and then taken high again. a7 a6 a5 a4 a3 a2 a1 a0 lsb msb a7 e high initiates one or more write cycles. low initiates one or more read cycles. a6 e must be low (zero) for normal operation. a5 e high signifies a clock/calendar location. low signifies a ram location. a0 a4 e remaining address bits (see figure 5). address and data data transfers can occur one byte at a time or in multibyte burst mode (see figures 16 and 17). after the MC68HC68t1 is enabled (ss = high), an address byte selects either a read or a write of the clock/calendar or ram. for a singlebyte read or write, one byte is transferred to or from the clock/cal - endar r egiste r o r r a m l ocatio n s pecifie d b y a n a ddress. additional reading or writing requires reenabling the device and providing a new address byte. if the MC68HC68t1 is not disabled, additional bytes can be read or written in a burst mode. each read or write cycle causes the clock/calendar register or ram address to automatically increment. incre - menting continues after each byte transfer until the device is disabled. a fte r i ncrementin g t o $ 1 f o r $ 9f , t h e a ddress wraps to $00 and continues if the ram is selected. when the clock/calendar is selected, the address wraps to $20 after incrementing to $32 to $b2. mosi ?????? ?????? ?????? ?????? ?????? ????????????? ????????????? ????????????? ????????????? ????????????? address byte data byte sck ss miso ?????? ?????? ?????? ?????? ?????????????????? ?????????????????? ?????????????????? ?????????????????? address byte mosi write read data byte figure 16. singlebyte transfer waveforms mosi ???? ???? ???? ???? ???? ???? ???? ???? address byte data byte 0 sck ss miso mosi write read data byte 1 data byte n ???? ???? ???? ???? address byte ?????????? ?????????? ?????????? ?????????? ????????? ????????? ????????? ????????? data byte 0 data byte 1 data byte n address byte address byte + 1 address byte + n w/r address figure 17. multiplebyte transfer waveforms
MC68HC68t1 motorola 19 application circuits bridge/ regulator low voltage ac line 100 k w 0.1 f 40 note 2 note 1 11 13 3 12 2 7 4 5 6 34 33 32 31 note 3 1 2 10 16 14 v dd 39 38 v dd v dd line v batt int v sys cpur ss sck mosi miso port sck mosi miso reset irq MC68HC68t1 mc68hc05c4 notes: 1. clock circuit driven by line input frequency. 2. poweron reset circuit included to detect power failure. 3. if an mc68hc1 1 mcu is used, delete the capacitor at the reset pin. xtal in figure 18. poweralwayson system por
MC68HC68t1 motorola 20 bridge/ regulator ac line MC68HC68t1 mc68hc05c4 v dd v dd por v batt line cpur reset v sys int irq clkout ss miso mosi sck osc 1 port (e.g., pc0) miso mosi sck note 2 note 1 note 3 v dd 100 k w 0.1 f 13 16 10 40 14 15 11 12 3 2 7 6 5 4 2 1 28 31 32 33 39 1 r charge notes: 1. the line input pin can sense when the switch opens by use of the power sense interrupt. the MC68HC68t1 crystal drives the clock input to the cpu using the clkout pin. on powerdown when v sys < v batt + 0.7 v , v batt powers the clock. a threshold detect activates an onchip p channel switch, connecting v batt to v dd . v batt always supplies power to the oscillator , keeping voltage frequency variation to a minimum. 2. for 32.768 khz oscillator , see figure 12. this configuration, when the MC68HC68t1 supplies the mcu clock, usually requires a 1 to 4 mhz clock. 3. if an mc68hc1 1 mcu is used, delete the capacitor at the reset pin. figure 19. externallycontrolled power system powersensing powerdown procedure a procedure for powerdown operation consists of the fol- lowing: 1. set power sense operation by writing bit 5 high in the interrupt control register. 2. when an interrupt occurs, the cpu reads the status register to determine the interrupt source. 3. sensing a power failure, the cpu does the necessary housekeeping to prepare for shutdown. 4. the cpu reads the status register again after several milliseconds to determine validity of power failure. 5. the c p u s et s p owerdow n ( bi t 6 ) a n d d isable s a ll interrupt s i n t h e i nterrup t c ontrol r egister w hen powerdown is verified. this causes the cpu reset and clock out pins to be held low and disconnects the serial interface. 6. when power returns and v sys rises above v batt + 0.7 v, powerup is initiated. the cpu reset is released and serial communication is established.
MC68HC68t1 motorola 21 notes: 1. see figure 12 for 32.768 khz operation. this configuration, where the MC68HC68t1 supplies the mcu clock, usually requires a 1 to 4 mhz crystal. 2. if an mc68hc1 1 mcu is used, delete the capacitor at the reset pin. bridge/ regulator ac line MC68HC68t1 mc68hc05c4 v dd v dd v batt line cpur reset clkout int ss spi osc 1 irq port spi 40 13 15 2 3 1 7 1 2 39 28 3 v dd por xtal 11 14 v sys pse 10 16 12 9 8 20 v ss v ss 0.1 f r charge 100 k w nc (eps) enabled power supply note 2 note 1 figure 20. rechargeable batterybackup system
MC68HC68t1 motorola 22 clock button enabled power MC68HC68t1 ignition v batt por xtal 2 mhz reset osc 1 irq spi port 12 9 2 3 7 3 1 39 2 27 8 20 28 40 16 11 12 v + 0.1 f note 1 v sys v dd line pse cpur clkout int spi ss 15 14 10 13 note 2 5 v reg 100 k mc68hc05c4 v ss port v dd notes: 1. the v sys and line inputs can be used to sense the ignition turning on and of f. an external switch is included to activate the system without turning on the ignition. also, the cmos cpu is not powered down with the system v dd , but is held in a low power reset mode during powerdown. when restoring power, the MC68HC68t1 enables the clkout pin and sets the pse and cpur pins high. 2. if an mc68hc1 1 mcu is used, delete the capacitor at the reset pin. 3. v oltage at pin must not exceed absolute maximum v in specification. v ss 1 figure 21. automotive system
MC68HC68t1 motorola 23 14 MC68HC68t1 v batt por sck 12 15 1 9 8 16 + 0.1 f v sys v dd xtal out cpur clkout pse 100 k v ss xtal in 10 ss int mosi miso line 10 pf* 3.0 v nonrechargeable battery r limit 215 k * 39 pf* v cc 1 k d block 32.768 khz 0.1 f 0.1 f 13 * actual values may vary , depending on recommendations of crystal manufacturer . 10 m 11 6 5 3 7 4 2 figure 22. nonrechargeable batterybackup system
MC68HC68t1 motorola 24 troubleshooting 1. the circuit works, but the standby current is well above the spec. how can the standby current be reduced? a. if using a 32.768 khz crystal, include a series resistor in the circuit per figure 12 of the data sheet. a good value to start with is 200 k . the signals at xt al out and xt al in pins should look similar to figure 23 when the correct value is selected. the sharp, clean edges on the xt al out pin reduces current on the totem pole drivers internal to the device. v batt 0 v 1 to 2 v pp xtal out xtal in approximately 30.52 s see note note: refer to item 8. figure 23. xtal waveforms b. connect the line pin to something other than v dd (e.g., v batt , v ss , v sys ) c. ensure that the poweronreset (por) has a time constant of at least 100 ms. d. ensure that there is a diode from v dd to + 5 v of the system, in batterybackup applications. see application circuits . 2. when power is applied, the clock does not start up nor does it hold data in the control registers. make sure the por circuit is connected and working. 3. the clock loses time, but the oscillator is tuned. do not make constant accesses to the clock. when a read or write cycle is started, the clock stops incrementing time. 4. when the part is power cycled, the clock loses all time and data. check the battery installation and ensure that a diode is in the circuit from v dd to + 5 v. 5. can a nonrechargeable lithium battery be used? yes, but the battery must have a large capacity . careful attention must be given if the end unit needs to be ul approved. the circuit of figure 22 is a good start. 6. able to read/write data to the ram but not to the clock reg - isters, or vice versa. there is a software problem. there is no internal dif fer- ence from reading/writing to the ram or clock locations. 7. how is the oscillator tuned? the best way to tune the oscillator is to set the clock out bits of the clock control register (bits 0, 1, and 2) to output the primary xt al frequency (000). the frequency can t he n b e m or e a ccuratel y m easure d f ro m t he clkout pin. this prevents the measuring device from loading t h e o scillato r c ircuit , w hic h m ay s hif t t h e f re- quency. 8. what is the accuracy of the oscillator? the oscillator accuracy is dependent on the quality of the crystal used. for every 1 ppm variance in crystal fre - quency, the clock gains or loses 2.6 seconds per month. 25 ppm is a typical spec for a crystal, which translates to 65 seconds per month. 9. can the line pin sense a dc failure? yes, the line input is threshold triggered in a window from one d iod e d ro p a bov e a n d b elo w v dd . i f s uppl y i s removed in the low cycle of a sine wave, the internal network pulls the line pin to within the threshold in a few milliseconds. in the absence of a dc voltage outside the v dd 0.7 v window , the internal network pulls the signal to within the window and triggers the interrupt. 10. can the v sys line be more than 0.5 v above v dd ? no. there is an esd protection network that causes a supply problem with this application. 11. the clkout , cpur , and pse pins do not go inactive when v dd and v sys are removed. the clkout , cpur , and pse are not active immediately when v dd and v sys is applied. the p roble m i s r elate d t o t h e p owe r u p p rocedure (batterybackup m od e o r s inglesuppl y m ode) . s ee these sections in the data sheet for more information.
MC68HC68t1 motorola 25 package dimensions p suffix plastic dip (dual inline package) case 64808 min min max max millimeters inches dim a b c d f g h j k l m s 18.80 6.35 3.69 0.39 1.02 0.21 2.80 7.50 0 0.51 19.55 6.85 4.44 0.53 1.77 0.38 3.30 7.74 10 1.01 0.740 0.250 0.145 0.015 0.040 0.008 0.110 0.295 0 0.020 0.770 0.270 0.175 0.021 0.070 0.015 0.130 0.305 10 0.040 notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: inch. 3. dimension alo to center of leads when formed parallel. 4. dimension abo does not include mold flash. 5. rounded corners optional. 6. 648-01 thru -07 obsolete, new standard 648-08. 2.54 bsc 1.27 bsc 0.100 bsc 0.050 bsc -a- b 1 8 9 16 f h g d 16 pl s c -t- seating plane k j m l 0.25 (0.010) t a m m dw suffix sog (small outline gullwing) package case 751g01 min min max max millimeters inches dim a b c d f g j k m p r 10.15 7.40 2.35 0.35 0.50 0.25 0.10 0 10.05 0.25 10.45 7.60 2.65 0.49 0.90 0.32 0.25 7 10.55 0.75 0.400 0.292 0.093 0.014 0.020 0.010 0.004 0 0.395 0.010 0.411 0.299 0.104 0.019 0.035 0.012 0.009 7 0.415 0.029 1.27 bsc 0.050 bsc notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimension a and b do not include mold protrusion. 4. maximum mold protrusion 0.15 (0.006) per side. -a- -b- p g 1 8 9 16 -t- d 16 pl k c seating plane m f j r x 45 8 pl 0.25 (0.010) b m m 0.25 (0.010) t b a m s s
MC68HC68t1 motorola 26 motorola reserves the right to make changes without further notice to any products herein. motorola makes no warranty , representation or guarantee regarding the suitability of its products for any particular purpose, nor does motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability , including without limitation consequential or incidental damages. at ypicalo parameters can and do vary in dif ferent applications. all operating parameters, including at ypicalso must be validated for each customer application by customer ' s technical experts. motorola does not convey any license under its patent rights nor the rights of others. motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body , or other applications intended to support or sustain life, or for any other application in which the failure of the motorola product could create a situation where personal injury or death may occur . should buyer purchase or use motorola products for any such unintended or unauthorized application, buyer shall indemnify and hold motorola and its of ficers, employees, subsidiaries, af filiates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly , any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that motorola was negligent regarding the design or manufacture of the part. motorola and are registered trademarks of motorola, inc. motorola, inc. is an equal opportunity/af firmative action employer . how to reach us: usa/europe : motorola literature distribution; japan : nippon motorola ltd.; tatsumispdjldc, toshikatsu otsuki, p.o. box 20912; phoenix, arizona 85036. 18004412447 6f seibubutsuryucenter, 3142 tatsumi kotoku, tokyo 135, japan. 0335218315 mfax : rmf ax0@email.sps.mot.com t ouchtone (602) 2446609 hong kong : motorola semiconductors h.k. ltd.; 8b tai ping industrial park, internet : http://designnet.com 51 ting kok road, tai po, n.t., hong kong. 85226629298 MC68HC68t1/d
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